By Topic

Modified majority logic decoding of cyclic codes in hybrid-ARQ systems

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
M. D. Rice ; Dept. of Electr. Eng., Brigham Young Univ., Provo, UT, USA ; S. B. Wicker

Reliability information provided by sets of orthogonal check sums in a majority logic decoder for block codes is used in a type-I hybrid automatic-repeat-request (ARQ) error control scheme. The reliability information is obtained through a simple modification of the majority logic decoding rule. It is shown that the reliability performance of Reed-Muller and other majority logic decodable codes can be substantially improved at the expense of a very small reduction in throughput. The simplicity of the decoding circuit permits implementation in systems with very high data rates

Published in:

IEEE Transactions on Communications  (Volume:40 ,  Issue: 9 )