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The impact of mobility modulation technology on device performance and reliability for sub-90nm SOI MOSFETs

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7 Author(s)
Yeh, W.-K. ; Department of Electrical Engineering, National University of Kaohsiung, Taiwan. No.700, Kaohsiung University Rd., Nan-Tzu Dist., Kaohsiung, Taiwan Phone:886-7-5919234, FAX: 886-7-5919374, e-mail: wkyeh@nuk.edu.tw ; Lai, C.M. ; Lin, C.-T. ; Fang, Y.-K.
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For nMOSFET, utilizing the high tensile stress gate capping layer (GC layer) and length of diffusion (LOD) to control the tensile and compressive stress in channel regions were developed. In this work, in order to investigate the interactive stress effects of GC layer film thickness, LOD and gate width on device's characteristic and hot-carrier reliability; devices with various GC layer (1100A, 700A, SiN380), LOD (0.45μm∼4.5μm) and width (0.18μm∼10μm) were fabricated. It is found that devices with 700A GC layer layer (appropriate tensile stress), 4.5μm LOD (low compressive stress) and 0.18μm gate width (narrow width) possess the better performance.

Published in:

Electron Devices and Solid-State Circuits, 2005 IEEE Conference on

Date of Conference:

19-21 Dec. 2005