By Topic

Coupled Monte Carlo-energy transport simulation with quasi-three-dimensional temperature analysis for SOI MOSFET

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

6 Author(s)
M. Koyanagi ; Res. Center for Integrated Syst., Hiroshima Univ. ; H. Kiba ; H. Kurino ; T. Hashimoto
more authors

Summary form only given. The authors evaluate a temperature-rise effect in short-channel SOI MOSFET using a device simulator that employs a quasi-3-D temperature analysis together with 2-D coupled Monte-Carlo-energy-transport analysis. It is shown that one can accurately simulate the drain current reduction and the negative output resistance in the saturation region due to the temperature rise in the channel. It is found that the temperature rise is significantly influenced by the layout design rule such as the wiring width, the contact hole size, and the gate-to-contact hole separation. Furthermore, it is revealed that the maximum electron temperature is reduced and consequently the drain breakdown voltage is increased due to the decreased number of hot carriers with higher energy when the temperature rise is taken into account

Published in:

IEEE Transactions on Electron Devices  (Volume:39 ,  Issue: 11 )