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For those adopting double data rate technology systems, the precise system timing plays a crucial role since both rising and falling edges of the system clock signal are used to sample the input data. Due to this requirement, it is necessary to accurately maintain the duty cycle of the clock signal at 50%. For a multistage clock buffer, a pulsewidth control loop (PWCL) circuit was therefore proposed to adjust the duty cycle of its output signal. This paper is aimed at introducing a new proposed differential PWCL (DPWCL) together with investigating its mechanism through a comprehensive theoretical analysis. By taking advantage of a differential topology, the dc offset in generating the control voltage can be removed thereby improving the duty cycle control accuracy. Moreover, the proposed DPWCL employs a low-pass filter to generate the reference voltage so that the DPWCL does not necessitate a 50% duty cycle reference clock.