By Topic

Fully integrated SONOS flash memory cell array with BT (body tied)-FinFET structure

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

9 Author(s)
Suk-Kang Sung ; Device Res. Team, Samsung Electron. Co., Gyeonggi-Do, South Korea ; Tae-Yong Kim ; Eun Suk Cho ; Cho, Hye Jin
more authors

Fully integrated SONOS memory cell arrays with BT (body tied)-FinFET structure have been fabricated successfully by using manufacturable NOR flash technology. The uniformity of threshold voltage (Vth) distribution of the fabricated FinFET SONOS cells is fairly better than that of conventional flash cells thanks to both the widening effective channel width of FinFET structure and negligible coupling interference of SONOS device. New two-step channel implantation process has been introduced for the compensation for the boron out-diffusion of a three-dimensional silicon fin structure. The measured FinFET SONOS cells with a two-step channel doping profile show the improved program and erase characteristics. For the improvement of program/erase and retention characteristics all together, we have investigated the modulation of erase bias condition with respect to back tunneling effect.

Published in:

Nanotechnology, IEEE Transactions on  (Volume:5 ,  Issue: 3 )