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Asynchronous Assertion Monitors for multi-Clock Domain System Verification

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3 Author(s)
Morin-Allory, K. ; TIMA Lab., Grenoble ; Fesquet, L. ; Borrione, D.

PSL is a standard formal language to specify logic and temporal properties in a declarative style, under the form of assertions. We defined a library of components, and an interconnection method to automatically synthesize hardware monitors that can be linked to a prototype of the design under verification, thus providing an efficient debugging platform. The existing tool produces on-line checkers that are clock synchronized with the monitored design. The on-going work aims at snooping the design with monitors built from asynchronous modules. The monitors are thus reliable in the case of truly asynchronous events, and become applicable to a wider range of verification tasks, notably the communications among globally asynchronous modules

Published in:

Rapid System Prototyping, 2006. Seventeenth IEEE International Workshop on

Date of Conference:

14-16 June 2006

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