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Performance Evaluation of an Adaptive FPGA for Network Applications

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2 Author(s)
Kachris, C. ; Dept. of Electr. Eng., Math. & Comput. Sci., Delft Univ. of Technol. ; Vassiliadis, S.

This paper presents the design and the performance evaluation of a coarse-grain dynamically reconfigurable platform for network applications. The platform consists of two MicroBlaze RISC processors and a number of hardware co-processors used for the processing of the packet's payload (DES encryption and Lempel-Ziv Compression). The co-processors can be connected either directly to the processors or using a shared bus. The type of the co-processors is dynamically reconfigured to meet the requirements of the network workload. The system has been implemented in the Xilinx Virtex II Pro FPGA platform and the network traces from real passive measurements have been used for performance evaluation. The use of dynamically reconfigurable co-processors for network applications shows that the performance speedup versus a static version varies from 12% to 35% in the best case and from 10% to 15% on average, depending on the variability in time and distribution of the network traffic

Published in:

Rapid System Prototyping, 2006. Seventeenth IEEE International Workshop on

Date of Conference:

14-16 June 2006