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New techniques for untestable fault identification in sequential circuits

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2 Author(s)
Syal, M. ; Bradley Dept. of Electr. & Comput. Eng., Virginia Polytech. Inst. & State Univ., Blacksburg, VA ; Hsiao, M.S.

This paper presents two low-cost fault-independent techniques that can be used to identify significantly more untestable faults than could be identified by earlier fault-independent techniques. A new theorem and an efficient implementation of the theorem for the purpose of identifying sequentially untestable faults are presented first. Unlike the single-fault theorem where the stuck-at fault is injected exclusively in the last time frame of the k-frame unrolled circuit, this theorem enables a fault injection in any time frame within the unrolled sequential circuit. To efficiently apply the authors' concept to untestable fault identification, sequential implications are used to extend the unobservability propagation of gates to multiple time frames during single-line conflict analysis. Then, a new technique called "maximizing local impossibilities" is proposed. This technique efficiently identifies multiple-node conflicting assignments by analyzing logical relationships local to Boolean gates in the circuit. Using this new concept in conjunction with a powerful implication engine enables identification of many more untestable faults that were missed by the single-line conflict-based approach. Since this approach concentrates on identifying conflicting combinations locally around each Boolean gate in the circuit, its complexity is linear in the size of the circuit. The application of these two proposed techniques to the International Symposium on Circuits and Systems (ISCAS) 1985 and ISCAS 1989 Sequential Benchmark Circuits showed a significant increase in the number of faults identified as untestable, at practically no overhead in both the memory and the execution time

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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:25 ,  Issue: 6 )