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Analysis and modeling of layout scaling in silicon integrated stacked transformers

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4 Author(s)
Biondi, T. ; Comput.-Aided Design & Design Solutions Group, STMicroelectronics, Catania, Italy ; Scuderi, Ang. ; Ragonese, E. ; Palmisano, G.

The analysis and modeling of monolithic stacked transformers fabricated in a high-speed silicon bipolar technology is addressed. On-wafer experimental measurements are employed to investigate the effect of layout scaling on transformer performance parameters (i.e., self-resonance frequency, magnetic coupling coefficient, and insertion loss). Based on this analysis, a wideband lumped model is developed, whose parameters are related to layout and technological data through closed-form expressions. Model accuracy is demonstrated by comparing simulated and measured S-parameters, coil inductance, magnetic coupling coefficient, and maximum available gain of several transformers with scaled layout geometry. The self-resonance frequency is also employed as a figure-of-merit to demonstrate model accuracy at very high frequency.

Published in:

Microwave Theory and Techniques, IEEE Transactions on  (Volume:54 ,  Issue: 5 )

Date of Publication:

May 2006

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