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Built-In Self-Test for PEs of Coarse Grained Dynamically Reconfigurable Devices

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2 Author(s)
K. Katoh ; Chiba University, Japan ; H. Ito

This paper proposes a BIST (built-in self test) method for testing the PEs (processing elements) of multi-context based dynamically reconfigurable processor. We use flip-flops existing in PEs to constitute the test circuit which has the function of LFSR (linear feedback shift register) and MISR (multiple input signature register) as DFT (design for testability). This method can reduce test execution time while maintaining the high rate of fault coverage. Evaluation of the proposed method examined on DRP-I, a coarse grained dynamically reconfiguration processor developed by NEC electronics in 2002 is presented. The number of test configurations and test execution time can be reduced 59.0% and 89.3% respectively compared to a deterministic test with 4.3% area overhead

Published in:

Eleventh IEEE European Test Symposium (ETS'06)

Date of Conference:

21-24 May 2006