By Topic

Built-In Self-Test for PEs of Coarse Grained Dynamically Reconfigurable Devices

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Katoh, K. ; Graduate Sch. of Sci. & Technol., Chiba Univ. ; Ito, H.

This paper proposes a BIST (built-in self test) method for testing the PEs (processing elements) of multi-context based dynamically reconfigurable processor. We use flip-flops existing in PEs to constitute the test circuit which has the function of LFSR (linear feedback shift register) and MISR (multiple input signature register) as DFT (design for testability). This method can reduce test execution time while maintaining the high rate of fault coverage. Evaluation of the proposed method examined on DRP-I, a coarse grained dynamically reconfiguration processor developed by NEC electronics in 2002 is presented. The number of test configurations and test execution time can be reduced 59.0% and 89.3% respectively compared to a deterministic test with 4.3% area overhead

Published in:

Test Symposium, 2006. ETS '06. Eleventh IEEE European

Date of Conference:

21-24 May 2006