By Topic

Distributed processing network architecture for reconfigurable computing

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Vallina, F.M. ; Dept. of Electr. & Comput. Eng., Illinois Inst. of Technol., Chicago, IL ; Oruklu, E. ; Saniie, J.

This paper introduces a set of rules and guidelines for the implementation of a distributed processing network (DPN) as the basis for a dynamic reconfigurable architecture targeted at improving the performance of microprocessor (muP) based systems in computationally intensive application domains. In order to provide the computation gains needed to improve upon the performance of the muP, the DPN architecture offers: 1) A low reconfiguration overhead, 2) A simple control interface, 3) Dynamic resource allocation, 4) Concurrent execution with dynamic reconfiguration, 5) Lower power dissipation than a muP executing the same computation kernel and, 6) Scalability to tackle tasks of varying resource requirements. DPN is currently targeted at realtime computationally intensive application domains such as compression, and signal transformations

Published in:

Electro Information Technology, 2005 IEEE International Conference on

Date of Conference:

22-25 May 2005