Cart (Loading....) | Create Account
Close category search window
 

Effects of parameter variations on timing characteristics of clocked registers

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Gada, P.R. ; Dept. of Electr. & Comput. Eng., Illinois Inst. of Technol., Chicago, IL ; Roberts, W.R. ; Velenis, D.

Violations in the timing constraints of a clocked register can cause a synchronous system to malfunction. The effects of parameter variations on the timing characteristics of registers that determine the timing constraints are investigated in this paper. The sensitivity of the setup time and data propagation delay on parameter variations is demonstrated for three different register designs that represent different tradeoff choices between performance and power dissipation. The robustness of each register design under variations in power supply voltage, temperature, and gate oxide thickness is discussed

Published in:

Electro Information Technology, 2005 IEEE International Conference on

Date of Conference:

22-25 May 2005

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.