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A dual-strained CMOS structure through simultaneous formation of relaxed and compressive strained-SiGe-on-insulator

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13 Author(s)
Bera, L.K. ; Inst. of Microelectron., Singapore, Singapore ; Mukherjee-Roy, M. ; Abidha, B. ; Agarwal, A.
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This letter reports on an integration of dual-strained surface-channel CMOS structure, i.e., tensile-strained Si n-MOSFET and compressive strained-SiGe p-MOSFET. This has been accomplished by forming the relaxed and compressive strained-SiGe layers simultaneously on an Si/SiGe-on-insulator (SOI) substrate, through varying SiGe film thicknesses, followed by a thermal condensation technique to convert the Si body into SiGe with different [Ge] concentration and with different strains (including the relaxed state). A thin Si film was selectively deposited over the relaxed SiGe region. The p-MOSFET in compressive (ε∼ -1.07%) strained- Si0.55Ge0.45 and the n-MOSFET in tensile-strained Si over the relaxed Si0.80Ge0.20 exhibited significant hole (enhancement factor ∼ 1.9) and electron (enhancement factor ∼ 1.6) mobility enhancements over the Si reference.

Published in:

Electron Device Letters, IEEE  (Volume:27 ,  Issue: 5 )