Referenced Items are not available for this document.
Leakage current in the nanometer regime has become a significant portion of power dissipation in CMOS circuits as threshold voltage, channel length, and gate oxide thickness scale downward. Various techniques are available to reduce leakage power in high-performance systems
Published in:
Micro, IEEE
(Volume:26
,
Issue:
2
)
Date of Publication: March-April 2006
- Page(s):
- 68 - 80
- ISSN :
- 0272-1732
- INSPEC Accession Number:
- 9007216
- Digital Object Identifier :
- 10.1109/MM.2006.39
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 24 April 2006
- Issue Date :
- March-April 2006
- Sponsored by :
- IEEE Computer Society
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