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A reduced multistage architecture for ATM networks

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2 Author(s)
Syed, M. ; Dept. of Comput. Eng. & Sci., Florida Atlantic Univ., Boca Raton, FL, USA ; Ilyas, M.

A novel communication switch architecture for ATM (asynchronous transfer mode) networks is presented. The speed of the proposed switch architecture is clock-rate-dependent. This architecture has a modular structure and provides a pipeline activity which reduces head-of-line blocking. As a result of using this architecture, the number of stages required is one half the number of stages used in switches today. This results in a reduction of delay to a maximum of 100% for the ideal case and to 20% on average and a reduction in throughput delay of 25% for the nonideal case when compared with a Banyan network. Because of its high degree of modularity, the architecture can be easily implemented using VLSI techniques

Published in:

Communications, 1991. ICC '91, Conference Record. IEEE International Conference on

Date of Conference:

23-26 Jun 1991