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A flipping structure for the discrete wavelet transform (DWT) was proposed by Huang et al., which aimed at shortening the critical path of the lifting-based one-dimensional (1-D) architecture and reducing the number of pipeline register used in 1-D architecture as well as the size of temporal buffer (TB) required in the line-based two-dimensional (2-D) architecture. In this paper, we explore the intrinsic relationship between the size of TB required in the line-based architecture for 2-D DWT (LBA2DDWT) and the number of registers used in a 1-D DWT module, and present a modified view on this issue that has been proposed by Huang et al. An improved method of mapping the registers used in 1-D DWT architecture to the TB required in LBA2DDWT is presented, which reduces more efficiently the size of memory required in LBA2DDWT than Huang's method. A parallel-based lifting scheme (PLS) for DWT and its VLSI architecture are presented. The proposed PLS of DWT not only reduces efficiently the critical path but also results in the equality of the forward discrete wavelet transform and inverse discrete wavelet transform implementations. Compared with Huang's method, the proposed PLS is more efficient in reducing critical path and/or the number of registers of VLSI implementation for 1-D DWT, and it can be concluded that the flipping structure of DWT is a special case of the PLS-based implementation.