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Design of 2.5V, 900MHz phase-locked loop (PLL) using 0.25μm TSMC CMOS technology

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4 Author(s)
Lee Ping Seng ; Sch. of Electr. & Electron. Eng., Univ. Sains Malaysia, Seberang Perai Selatan, Malaysia ; Zulkifli, T.Z.A. ; Noh, N.M. ; Saibon, B.

In this paper, a 2.5V, operating at 900MHz phase-locked loop implemented in 0.25μm TSMC CMOS process technology is presented. A high speed PFD is implemented using true-single-phase clock (TSPC) technique which manages to operate up to 1.1 GHz. VCO using ring oscillator with dual-delay path scheme is implemented to achieve 900MHz operation frequency with wider tuning range. The PLL manage to lock within 100ns. The PLL implementation only needs 67 transistors and consumes 23.81mW.

Published in:

Semiconductor Electronics, 2004. ICSE 2004. IEEE International Conference on

Date of Conference:

7-9 Dec. 2004