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As the chip geometry continues to shrink into nanometer scale, and more functionality are being added to the chip, power consumption is emerging as the no. 1 limiting source of design constraints. With the technology migrating to 90nm processing, new and more tightened design constraints have emerged rendering power reduction battle even more complex. In this paper, we present a clock gating power methodology that ensures power closure without significant expense to the timing, area and clock constraints. This methodology has been implemented in our first 90nm network processor unit. The results show close to 50% power saving and area reduction of 15% achieved.