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ASIC design of a Kohonen neural network microchip

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2 Author(s)
Rajah, A. ; Dept. of Microelectron. & Comput. Eng., Univ. Teknologi Malaysia, Johor Bahru, Malaysia ; Khalil Hani, M.

This paper discusses the Kohonen neural network (KNN) processor and its KNN computation engine microchip. The ASIC design of the KNN processor adopts a novel implementation approach whereby the computation of the KNN algorithm is performed on the custom ASIC microchip and its operations are governed by a FPGA based controller. Thus, the ASIC implementation of the KNN processor is derived through integration between a custom ASIC and FPGA. The 3.3V AMI 0.5μm C05M-D process technology was used to achieve the VLSI design of the computation engine microchip and the entire design adopted the BBX cell based methodology, which is a viable alternative to conventional ASIC methodology.

Published in:

Semiconductor Electronics, 2004. ICSE 2004. IEEE International Conference on

Date of Conference:

7-9 Dec. 2004

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