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Memory-efficient architecture for JPEG 2000 coprocessor with large tile image

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2 Author(s)
Bing-Fei Wu ; Dept. of Electr. & Control Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan ; Chung-Fu Lin

The experimental results show that using a larger tile size to perform JPEG 2000 coding results in better image quality (i.e., greater than or equal to 256 /spl times/ 256 tile image). However, processing large tile images also requires relatively high memory for the hardware implementation. For example, it would require tile memory of 256 K words to support the process of a 512 /spl times/ 512 tile image in the straightforward architecture. To reduce hardware resources, we have proposed the quad code-block (QCB) -based discrete wavelet transform method to reduce the size of tile memory by a factor of 4. In this paper, the remaining 1/4 tile memory can be further reduced through two approaches: the zero-holding extension with slight image degradation and the QCB-block size extension without any image degradation. That is, it only requires 12 K words tile memory to support the process of 512 /spl times/ 512 tile image by using zero-holding extension, and 13.58 K words memory through QCB-block size extension. The low memory requirement makes the on-chip memory practicable.

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Circuits and Systems II: Express Briefs, IEEE Transactions on  (Volume:53 ,  Issue: 4 )