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Impact of STI on the reliability of narrow-width pMOSFETs with advanced ALD N/O gate stack

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9 Author(s)
S. S. Chung ; Dept. of Electron. Eng., Nat. Chiao-Tung Univ., Hsinchu, Taiwan ; Chang-Hua Yeh ; Hsin-Jung Feng ; Chao-Sung Lai
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For the first time, a shallow trench isolation (STI)-induced enhanced degradation in pMOSFETs for ultrathin gate oxide devices has been observed. The ID degradation is enhanced as a reduction in the gate width and the hot carrier (HC) or negative bias temperature instability (NBTI) effect. Extensive studies have been compared for atomic layer deposition (ALD)-grown and plasma-treated oxide pMOSFETs. Different temperature dependences were observed. At room temperature, hole trap is dominant for the device degradation, in which hole-trap-induced VT is significant, whereas at high temperature under NBTI stress, interface trap becomes more significant, which dominates the device ID degradation. In addition, the VT rolloff can be modeled as a width narrowing effect specifically for STI. More importantly, the NBTI-induced interface/oxide traps are strongly related to the hydrogen and N2 content in the gate oxide formation process. The interface trap generation is suppressed efficiently using the ALD-grown gate oxide. These results provide a valuable guideline for the understanding of the HC and NBTI reliabilities in an advanced ALD-grown gate oxide processes/devices.

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IEEE Transactions on Device and Materials Reliability  (Volume:6 ,  Issue: 1 )