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A 5.7-GHz low-power and high-gain 0.18-/spl mu/m CMOS double-balanced mixer for WLAN

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4 Author(s)
Liao, C.-H. ; Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan ; Chu, Y.-K. ; Huang, D.-R. ; Chuang, H.-R.

This paper presents a low-power and high-gain 5.7 GHz CMOS double-balanced mixer for an IEEE 802.11a WLAN application. The RF input frequency of the mixer is 5.725 ~ 25 GHz, LO is 5.265 ~ 5.325 GHz, IF is at 480 MHz. The mixer is fabricated with the 0.18 mum 1P6M standard CMOS process. The die size is 0.627 times 0.649 mm2. The measurements are performed using an FR-4 PCB test fixture. The fabricated mixer exhibits a conversion gain of 11 dB, noise figure of 12.8 dB, and input P1dB -16.4 dBm. The DC consumption current is 2.0 mA /1.0 mA for the core/buffer amplifier at VDD = 1.8 V

Published in:

Wireless Technology, 2005. The European Conference on

Date of Conference:

3-4 Oct. 2005