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Accelerating diagnostic fault simulation using z-diagnosis and concurrent equivalence identification

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3 Author(s)
Seshadri, B. ; Purdue Univ., West Lafayatte, IN ; Yu, X. ; Venkataraman, S.

We propose techniques to speed up diagnostic fault simulation for circuits without full-scan which may need multi-cycle tests. First, we introduce the concept of z-sets for circuits without full scan and show how z-sets can be used in a preprocessing step to improve the performance of diagnostic fault simulation. Further, an implementation of an equivalence identification tool that executes concurrently with diagnostic fault simulation is described along with methods to increase its efficiency by prioritizing fault pair selection and reducing interprocess communication. Finally, a combination of both these techniques is analyzed and the performance benefit is presented. Experimental results on ISCAS'89 benchmarks and industrial circuits indicate that diagnostic fault simulation is substantially faster by 20.6 to 46.9% when z-sets are used along with concurrent equivalent fault identification

Published in:

VLSI Test Symposium, 2006. Proceedings. 24th IEEE

Date of Conference:

April 30 2006-May 4 2006