By Topic

Parametric fault diagnosis for analog circuits using a Bayesian framework

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Fang Liu ; Dept. of Electr. & Comput. Eng., Duke Univ., Durham, NC, USA ; Nikolov, P.K. ; Ozev, S.

In this paper, we present a parametric fault diagnosis approach for analog/RF circuits based on a Bayesian framework. The Bayesian fault diagnosis requires extensive statistical profiling which is enabled by a an efficient hierarchical process variability analysis. Both DC and AC parameters are used as measurements to provide maximum diagnostic resolution. A sensitivity guided test input selection scheme is used to determine the measurement attributes that are most likely to distinguish among the faults. Fault dictionaries are constructed using parametric faults at the transistor level that have both marginal and higher deviations. During the diagnosis step, additional online profiling helps increase the diagnostic resolution. Experiments on a transistor level amplifier circuit confirms that the approach is accurate in terms of statistical attributes and most deviations in layout and process level parameters can be correctly diagnosed.

Published in:

VLSI Test Symposium, 2006. Proceedings. 24th IEEE

Date of Conference:

30 April-4 May 2006