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A new ATPG method for efficient capture power reduction during scan testing

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8 Author(s)
Xiaoqing Wen ; Dept. of Comput. Sci. & Eng., Kyushu Inst. of Technol., Iizuka ; Kajihara, S. ; Miyase, K. ; Suzuki, T.
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High power dissipation can occur when the response to a test vector is captured by flip-flops in scan testing, resulting in excessive JR drop, which may cause significant capture-induced yield loss in the DSM era. This paper addresses this serious problem with a novel test generation method, featuring a unique algorithm that deterministically generates test cubes not only for fault detection but also for capture power reduction. Compared with previous methods that passively conduct X-filling for unspecified bits in test cubes generated only for fault detection, the new method achieves more capture power reduction with less test set inflation. Experimental results show its effectiveness

Published in:

VLSI Test Symposium, 2006. Proceedings. 24th IEEE

Date of Conference:

April 30 2006-May 4 2006