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Through-wafer interconnection by deep damascene process for MEMS and 3D wafer level packaging

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6 Author(s)
N. Ranganathan ; Inst. of Microelectron., Singapore, Singapore ; Jiang Ning ; Liao Ebin ; C. S. Premachandran
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A deep silicon copper via process technology by damascene copper electroplating process has been developed and characterized for realizing through-wafer copper interconnection for MEMS and 3D wafer level packaging application. The paper further discusses various factors that affect the formation of deep silicon vias structures by using time-multiplexed inductive coupled plasma etch process, also known as the BOSCH process. In this work we have evaluated copper vias of various widths ranging from 5 to 50 mum with depths of 10 to 100 mum. A special test structure has been developed with copper vias modified to form opposing pairs of fingers of a comb structure. These finger structures are then electrically characterized under various thermal and voltage stress conditions

Published in:

2005 7th Electronic Packaging Technology Conference  (Volume:1 )

Date of Conference:

7-9 Dec. 2005