Through-wafer interconnection by deep damascene process for MEMS and 3D wafer level packaging

A deep silicon copper via process technology by damascene copper electroplating process has been developed and characterized for realizing through-wafer copper interconnection for MEMS and 3D wafer level packaging application. The paper further discusses various factors that affect the formation of deep silicon vias structures by using time-multiplexed inductive coupled plasma etch process, also known as the BOSCH process. In this work we have evaluated copper vias of various widths ranging from 5 to 50 /spl mu/m with depths of 10 to 100 /spl mu/m. A special test structure has been developed with copper vias modified to form opposing pairs of fingers of a comb structure. These finger structures are then electrically characterized under various thermal and voltage stress conditions.