Skip to Main Content
In this paper, we present a transceiver architecture that incorporates an ultra-high performance software programmable SIMD based processor for digital communications in order to perform many of the intensive baseband processing modules required by a software defined radio (SDR). The parallel processor is used as the core of the transceiver and its usage for physical layer functions in wireless communications is evaluated. The parallel core consists of an array of identical processing elements and a reconfigurable intercommunication network for concurrent data processing. Complete high level software programmability of the core provides the desired flexibility over ASIC based systems and may reduce the time-to-market period and overall design costs. The array-based architecture also addresses the high speed performance requirements typically lacking in DSP architectures for processing realtime data streaming from the RF front end. It also matches FPGA technology in terms of raw performance while incorporating complete reconfigurability to realize the goal of multimode systems.