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To integrate future 3D electronic circuits that contain vertical interconnects, the cross sectional profile of each connecting via must be precisely known. Through silicon vias (TSVs) are one approach to vertical interconnects and the subject of this paper. To investigate these vias, a small wafer sample is mechanically polished and viewed using scanning electron microscopy (SEM). The vias that were formed in this research were 4-8 μm in diameter and 20-30 μm deep. To analyze the characteristics of the vias, the average surface variation on the edge of polished samples needs to be 100 nanometers or less. In this research, it was found that an average surface variation of less than 10 nm can be achieved within 45 minutes of polishing by utilizing a specially designed sample holder. This polishing procedure offers benefits over other sample preparation procedures such as epoxy potting and polishing because this new method is reproducible, reliable and beneficial to overall sample analysis.