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This paper describes a hardware controller that reduces active power consumption in standard cell ASICs by adaptively adjusting the supply voltage to varying performance requirements. The hardware controller is embedded on the same die as the application ASIC. It consists of a hardware performance monitor, control logic and a serial interface logic. These functions combine to form a closed-loop that regulates the speed of the application. The proposed scheme has been implemented in a video processor designed in a 0.18 μm standard CMOS process. Experimental results demonstrate operation over a wide frequency range of 6 MHz to 48 MHz and up to 60% power savings when compared to an open-loop scheme.