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A 65nm random and systematic yield ramp infrastructure utilizing a specialized addressable array with integrated analysis software

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9 Author(s)
Karthikeyan, M. ; IBM Syst. & Technol. Group, Hopewell Junction, NY, USA ; Fox, S. ; Cote, W. ; Yeric, G.
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This paper describes a yield learning infrastructure that has been developed and deployed to help rapidly ramp 65nm random and systematic yield. This infrastructure consists of a 4Mb addressable-array test circuit with > 8000 unique test structures along with customized software and automated analysis routines to distill the large datasets generated. Examples of the successful application of this methodology are provided.

Published in:

Microelectronic Test Structures, 2006. ICMTS 2006. IEEE International Conference on

Date of Conference:

6-9 March 2006