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A DRAM/SRAM memory scheme for fast packet buffers

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5 Author(s)
Garcia-Vidal, J. ; Comput. Archit. Dept., Tech. Univ. of Catalonia, Barcelona, Spain ; March, M. ; Cerda, L. ; Corbal, J.
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We address the design of high-speed packet buffers for Internet routers. We use a general DRAM/SRAM architecture for which previous proposals can be seen as particular cases. For this architecture, large SRAMs are needed to sustain high line rates and a large number of interfaces. A novel algorithm for DRAM bank allocation is presented that reduces the SRAM size requirements of previously proposed schemes by almost an order of magnitude, without having memory fragmentation problems. A technological evaluation shows that our design can support thousands of queues for line rates up to 160 Gbps.

Published in:

Computers, IEEE Transactions on  (Volume:55 ,  Issue: 5 )

Date of Publication:

May 2006

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