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Switch Scheduling and Network Design for Real-Time Systems

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3 Author(s)
Gopalakrishnan, S. ; University of Illinois at Urbana-Champaign ; Caccamo, M. ; Lui Sha

The rapid need for high bandwidth and low latency communication in distributed real-time systems is driving system architects towards high-speed switches developed for high volume data transfer on the Internet. These switches employ complex scheduling algorithms for transferring data cells from the input line to the output line. From a real-time systems perspective, it is necessary to understand the behavior of these switching algorithms and obtain worst-case delay bounds for message transfer across these switches. Many researchers have derived average-case delay bounds for switching algorithms but mission-critical systems require guarantees for the worst-case. In this context, we derive upper bounds on cell delays across commonly available switches. Our bounds provide a starting point for research in this direction. Moreover, we use the delay bounds to construct low-cost networks of switches given a set of processors and their real-time communication requirements. Experiments with the heuristic algorithm that we propose for network design have produced encouraging results. Importantly, the algorithm is independent of the delay analysis technique and better techniques can be incorporated trivially. By addressing the network design problem, we hope to transform the system architecting process from a manual, ad-hoc operation to a simple and automated step that will result in better designs and cost savings.

Published in:

Real-Time and Embedded Technology and Applications Symposium, 2006. Proceedings of the 12th IEEE

Date of Conference:

04-07 April 2006

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