By Topic

Yield enhancement methodology for CMOS standard cells

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

8 Author(s)

In order to maximize the yield of random logic in today's advanced deep sub-micron CMOS technologies we have developed a complete yield enhancement methodology for CMOS standard cells. This methodology based on a test vehicle approach covers design, industrial test, data collection and volume analysis, design debug, failure location and analysis. It has proven to be successful on three consecutive technology nodes down to 65nm. This paper explains the methodology and demonstrate the results and benefits of this work through illustrated examples

Published in:

Quality Electronic Design, 2006. ISQED '06. 7th International Symposium on

Date of Conference:

27-29 March 2006