On optimizing scan testing power and routing cost in scan chain design

With advanced VLSI manufacturing technology in deep submicron (DSM) regime, we can integrate entire electronic systems on a single chip (SoC). Due to the complexity in SoC design, circuit testability becomes one of the most challenging works. Without careful design in scan cell placement and chain ordering, circuits consume much more power in test mode operation than that in normal functional mode. This elevated testing power may cause problems including overall yield lost and instant circuit damage. In this paper, we present an approach to simultaneously minimizing power and routing cost in scan chain reordering after cell placement. We formulate the problem as a traveling salesman problem (TSP), different cost evaluation from (Bonhomme et al., 2004), (Bonhomme et al., 2003), and apply an efficient heuristic to solve it. The experimental results are encouraging. Compared with a recent result in (Bonhomme et al., 2004), which uses the approach with clustering overhead, we obtain up to 10% average power saving under the same low routing cost Furthermore, we obtain 57% routing cost improvement under the same test power consumption in s9234, one of ISCAS'89 benchmarks. We collaborate multiple scan chains architecture with our methodology and obtain good results as well