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Analysis of pulse signaling for low-power on-chip global bus design

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2 Author(s)
Min Chen ; Arizona State Univ., Phoenix, AZ, USA ; Yu Cao

Pulse signaling is proposed for on-chip global bus design to reduce dynamic power consumption. To maximize power saving, shorter pulse width and longer propagation length are preferred. In this work, a complete set of analytical models are developed for pulse propagation along RLC lines. These models connect line geometries and electrical properties of an input pulse with several important design metrics, such as delay, pulse width, maximum propagation length, and power saving. Excellent model accuracy is achieved as compared to SPICE simulations. These models can be easily implemented into design tools to facilitate the optimization of pulse signaling on lossy on-chip global buses. Furthermore, pulse signaling can be integrated with a time-division scheme to further reduce power consumption. Using the newly developed models, it is demonstrated that more than 70% dynamic power can be saved in this scheme in on-chip bus design

Published in:

7th International Symposium on Quality Electronic Design (ISQED'06)

Date of Conference:

27-29 March 2006