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Constructing current-based gate models based on existing timing library

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3 Author(s)
Kahng, A.B. ; Dept. of Comput. Sci. & Eng., California Univ. at San Diego, La Jolla, CA ; Bao Liu ; Xu, X.

Current-based gate modeling achieves a new level of accuracy in nanoscale design timing and signal integrity analysis. However, to generate current-based gate models requires additional pre-characterization of the gate, e.g., in the form of a new or an extended timing library format. We construct current-based gate models based on the existing Liberty timing library format without further pre-characterization. We present an inverse problem formulation, and propose to solve the problem by quadratic polynomial regression. Our constructed current-based gate models find applications in timing, power, and signal integrity verifications for improved accuracy in library-compatible flows, e.g., to include power supply voltage drop effect in gate delay calculation without further pre-characterization, to calculate gate supply current, etc. Our experimental results show our constructed current-based gate models achieve slightly less accurate results, e.g., within 4.6%(8.6%), than pre-characterized current-based gate models, e.g., within 4.3%(4.4%), of SPICE results in gate delay calculation for ideal (degraded) power supply voltage, and accurate gate supply current calculation

Published in:

Quality Electronic Design, 2006. ISQED '06. 7th International Symposium on

Date of Conference:

27-29 March 2006