Work in Progress – A Rapid Design Methodology for FPGA-based Processor Platform Design Education

A rapid register-transfer level (RTL) embedded processor platform design methodology that is included as an educational tool for a special topic is introduced. In the special topic, rapid digital system design from digital fundamentals to processor platforms is practiced using a top-down design methodology with both Verilog hardware description language (HDL) and VHDL. In addition, all of the RTL design and verification processes can be rapidly and systematically performed through the methodology. Furthermore, a hierarchical RTL post-simulation verification methodology and a supporting tool can provide a rapid, flexible, and affordable verification environment for the field-programmable gate array (FPGA)-based embedded processor platform developed in the classroom. This methodology leads to the rapid development of embedded processor platforms for use in academia