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Design of a 1GHz Digital PLL Using 0.18mu m CMOS Technology

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1 Author(s)
Janardhan, H. ; Dept. of Electr. Eng., California State Univ., Long Beach, CA

A digital phase-locked loop (DPLL) is designed and is shown to have 1GHz operation with lock time of 643.36ns. The lock time was reduced by adjusting the charge pump current and the loop filter capacitor. There was a trade-off between the lock time, loop filter capacitor, and ripples on the output of the VCO. Design procedures and simulation results are illustrated

Published in:

Information Technology: New Generations, 2006. ITNG 2006. Third International Conference on

Date of Conference:

10-12 April 2006