A novel hardware implementation of MP3 decoder for low power and minimum chip size

The structure presented in this paper is for the hardware implementation of MP3 decoder. The purpose is to achieve a controller IC with low power consumption, small chip size and flexible choice of peripheral flash memory. DSP is not required in this design, but a simple 8-bit microcontroller is used instead. The specific hardware circuits can lower the system frequency to save power, and some techniques are applied to reduce the embedded memory.