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A novel hardware implementation of MP3 decoder for low power and minimum chip size

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2 Author(s)
Yang Jan-Ti ; Ta Hwa Inst. of Technol., Hsinchu ; Jun-Ming Yu

The structure presented in this paper is for the hardware implementation of MP3 decoder. The purpose is to achieve a controller IC with low power consumption, small chip size and flexible choice of peripheral flash memory. DSP is not required in this design, but a simple 8-bit microcontroller is used instead. The specific hardware circuits can lower the system frequency to save power, and some techniques are applied to reduce the embedded memory

Published in:

ASIC, 2005. ASICON 2005. 6th International Conference On  (Volume:2 )

Date of Conference:

24-0 Oct. 2005