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A fast algorithm for power optimization using multiple voltages in data path synthesis

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4 Author(s)
Jianfeng Huang ; Dept. of Comput. Sci. & Technol., Tsinghua Univ., Beijing ; Jinian Bian ; Zhipeng Liu ; Yunfeng Wang

In this paper, we propose a fast iterative improvement algorithm to optimize power consumption during data path synthesis using multiple supply voltages and threshold voltages. We do scheduling, binding and voltage assignment simultaneously by applying some heuristic strategies such that power consumption can be quickly optimized to a considerable level. Experimental results on a number of standard benchmarks using three supply voltage levels and three threshold voltage levels show that an average power saving of 36.186% can be obtained compared to using a single supply voltage level (with a time constraint of 1.2 times the critical path delay and a resource constraint of two function unit each type)

Published in:

ASIC, 2005. ASICON 2005. 6th International Conference On  (Volume:2 )

Date of Conference:

24-0 Oct. 2005