By Topic

A high-performance low-power 2D 8×8 IDCT processor with asynchronous pipeline

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Xu Ma ; Inst. of Microelectron., Chinese Acad. of Sci., Beijing, China ; Jian Gao ; Jie Chen

This paper presents a high-performance low-power 2D IDCT processor for video applications. Based on multiply-accumulator architecture, the processor can meet the high-speed requirement of HDTV. To save power consumption, the processor employs asynchronous pipeline in which local clocks are enabled only when there is an operation to perform. Compared with conventional synchronous pipelined design, the proposed design exhibits an average power saving of 40%.

Published in:

ASIC, 2005. ASICON 2005. 6th International Conference On  (Volume:1 )

Date of Conference:

24-27 Oct. 2005