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This paper presents a high-performance low-power 2D IDCT processor for video applications. Based on multiply-accumulator architecture, the processor can meet the high-speed requirement of HDTV. To save power consumption, the processor employs asynchronous pipeline in which local clocks are enabled only when there is an operation to perform. Compared with conventional synchronous pipelined design, the proposed design exhibits an average power saving of 40%.
ASIC, 2005. ASICON 2005. 6th International Conference On (Volume:1 )
Date of Conference: 24-27 Oct. 2005