By Topic

A new HW/SW co-design methodology to generate a system level platform based on LISA

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)

A new methodology to build HW/SW co-design platform based on machine description language-LISA is presented in this paper. The most important aims of this method are to model a retargetable processor at the early stage of HW/SW co-design so as to get optimum results for system level analysis. Also it helps to speed up time-to-market and ease manual work. Furthermore, this method is flexible and can be used for designing either general purpose processor (GPP) or application specified instruction-set processor (ASIP). With the design flow, we have been able to verify and evaluate one VLIW processor - SuperV2 in less than one month

Published in:

ASIC, 2005. ASICON 2005. 6th International Conference On  (Volume:1 )

Date of Conference:

24-0 Oct. 2005