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Design methodology of low power JPEG2000 codec exploiting dual voltage scaling

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4 Author(s)
Yicong Meng ; Dept. of Electron. Eng., Tsinghua Univ., Beijing, China ; Leibo Liu ; Li Zhang ; Zhihua Wang

This paper proposed a novel dual voltage scaling layout architecture and a design methodology of low power JPEG2000 codec exploiting dual voltage scaling. Fabricated in SMIC 0.18μm 1P6M standard CMOS technology, this codec is capable of JPEG2000 compression/decompression with a 1280×1024 pixel (YUV422 full color) at 20 frames/s employing 100MHz operation frequency. And the power consumption is 465mW @ 1.8V and 100MH. Applied with dual voltage scaling technique, the power dissipation is reduced by 28.5%.

Published in:

2005 6th International Conference on ASIC  (Volume:1 )

Date of Conference:

24-27 Oct. 2005