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An integrated reset/pulse pile-up rejection circuit for pixel readout ASICs

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11 Author(s)

We present a compact and low power integrated circuit designed to control the reset and perform pulse pile-up rejection in multi-channel spectroscopic-grade ASICs. The circuit has been implemented in a 0.35 mum CMOS technology using an area of 60times80 mum2 and null static power consumption. These features make this circuit suitable to be embedded into the front-end readout cells for spectroscopy/imaging X- and gamma-ray pixel detectors

Published in:

Nuclear Science, IEEE Transactions on  (Volume:53 ,  Issue: 1 )

Date of Publication:

Feb. 2006

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