Cart (Loading....) | Create Account
Close category search window

An integrated reset/pulse pile-up rejection circuit for pixel readout ASICs

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

11 Author(s)

We present a compact and low power integrated circuit designed to control the reset and perform pulse pile-up rejection in multi-channel spectroscopic-grade ASICs. The circuit has been implemented in a 0.35 mum CMOS technology using an area of 60times80 mum2 and null static power consumption. These features make this circuit suitable to be embedded into the front-end readout cells for spectroscopy/imaging X- and gamma-ray pixel detectors

Published in:

Nuclear Science, IEEE Transactions on  (Volume:53 ,  Issue: 1 )

Date of Publication:

Feb. 2006

Need Help?

IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.