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A matrix amplifier in 0.18-/spl mu/m SOI CMOS

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2 Author(s)
Jinho Park ; Marvel Semicond. Inc., Santa Clara, CA ; Allstot, D.J.

A fully integrated matrix amplifier with two rows and four columns (2-by-4) fabricated in a three-layer metal 0.18-mum silicon-on-insulator (SOI) CMOS process is presented. It exhibits an average pass-band gain of 15 dB and a unity-gain bandwidth of 12.5 GHz. The input and output ports are matched to 50 Omega using m-derived half sections; the measured S11 and S22 values exceed -7 and -12 dB, respectively. Integrated in 2.0times2.9mm2 , it dissipates 233.4 mW total from 2.4- and 1.8-V power supplies

Published in:

Circuits and Systems I: Regular Papers, IEEE Transactions on  (Volume:53 ,  Issue: 3 )

Date of Publication:

March 2006

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