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A CMOS-process-compatible backside inductively coupled-plasma (ICP) dry etching technology to form deep trenches underneath the inductors of RF ICs is developed to enhance the performance of RF ICs with on-chip inductors. A 1-12.6-GHz CMOS distributed amplifier (DA) was designed and implemented in a standard CMOS process. The DA exhibits good input 1-dB compression point (P1 dB) of -2 dBm and input third intercept point of 7 dBm both at 2.4 and 5.8 GHz. The authors demonstrate that a significant improvement in power gain (S21) and noise figure (NF) can be achieved by conducting the proposed backside ICP dry etching to selectively remove the silicon underneath the inductors of the DA. The result shows that a 1.06-dB increase in S21 (from 9.7 to 10.76 dB) and a 0.87-dB decrease (from 5.51 to 4.64 dB) in NF are achieved at 5.8 GHz mainly due to the improvement of the quality factor of the inductors in the DA. This means that this backside ICP dry-etching technique is very promising for system-on-a-chip applications.