Skip to Main Content
This paper presents an efficient heuristic algorithm, which employs successive partitioning and grid-refinement scheme, for designing the power distribution network of a chip. In an iterative procedure, the chip area is recursively bipartitioned, and the wire pitches and the wire widths of the power grid in the partitions are repeatedly adjusted to meet the voltage drop and current-density specifications. By using the macromodels of the power grid constructed in the previous levels of partitioning, the scheme ensures that a small global power grid system is simulated in each iteration. The idea is based on the notion that due to the locality properties of the power grid, the effects of distant nodes and sources can be modeled more coarsely than the nearby elements, and include practical methods that enhance the convergence of the iterative conjugate-gradient-based solution engine that is used in each step. Finally, a postprocessing step at the end of the optimization is employed to maximize the alignment of wires in adjacent partitions. The effectiveness of the scheme is demonstrated by designing various power grids with real circuit parameters and realistic input current values. The proposed algorithm is able to design power grids comprising thousands of wires and more than a million electrical nodes in about 6 to 14 min. When compared to a multigrid-based power grid design scheme, it is found to save about 5% to 10% of wire area, and on an average is 12% faster.