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Technology mapping algorithm targeting routing congestion under delay constraints

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3 Author(s)
Shelar, R.S. ; Enterprise Microprocessors Group, Intel Corp., Hillsboro, OR, USA ; Saxena, P. ; Sapatnekar, S.S.

Routing congestion has become a serious concern in today's very-large-scale-integration designs. To address this, the authors propose a technology mapping algorithm that minimizes routing congestion under delay constraints in this paper. The algorithm employs a dynamic-programming framework in the matching phase to generate probabilistic congestion maps for all the matches. These congestion maps are then utilized to minimize routing congestion during the covering, which preserves the delay optimality of the solution using the notion of slack. Experimental results on benchmark circuits in a 100-nm technology show that the algorithm can improve track overflows significantly as compared to conventional technology mapping while satisfying delay constraints.

Published in:

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:25 ,  Issue: 4 )