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A 22-gb/s PAM-4 receiver in 90-nm CMOS SOI technology

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9 Author(s)
T. Toifl ; IBM Zurich Res. Lab., Ruschlikon, Switzerland ; C. Menolfi ; M. Ruegg ; R. Reutemann
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We report a receiver for four-level pulse-amplitude modulated (PAM-4) encoded data signals, which was measured to receive data at 22 Gb/s with a bit error rate (BER) <10-12 at a maximum frequency deviation of 350 ppm and a 27-1 PRBS pattern. We propose a bit-sliced architecture for the data path, and a novel voltage shifting amplifier to introduce a programmable offset to the differential data signal. We present a novel method to characterize sampling latches and include them in the data path. A current-mode logic (CML) biasing scheme using programmable matched resistors limits the effect of process variations. The receiver also features a programmable signal termination, an analog equalizer and offset compensation for each sampling latch. The measured current consumption is 207 mA from a 1.1-V supply, and the active chip area is 0.12 mm2.

Published in:

IEEE Journal of Solid-State Circuits  (Volume:41 ,  Issue: 4 )