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Notice of Violation of IEEE Publication Principles
A multi-rate 9.953-12.5-GHz 0.2-μm SiGe BiCMOS LC oscillator using a resistor-tuned varactor and a supply pushing cancellation circuit

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1 Author(s)
Maxim, A. ; Silicon Labs., Austin, TX, USA

Notice of Violation of IEEE Publication Principles

"A multi-rate 9.953-12.5-GHz 0.2-μm SiGe BiCMOS LC oscillator using a resistor-tuned varactor and a supply pushing cancellation circuit"
by Maxim, A.
in the IEEE Journal of Solid-State Circuits,
Volume 41, Issue 4, April 2006 Page(s):918 - 934

After careful and considered review, it has been determined that the above paper is in violation of IEEE's Publication Principles.

Specifically, the paper contains information that Adrian Maxim admits had been falsified. In response to an inquiry on this misconduct, Mr. Maxim acknowledged that the following people who have been listed as co-authors on several of his papers are fabricated names and that he is the only author:

C. Turinici, D. Smith, S. Dupue

Additionally, in papers by Mr. Maxim that have co-authors other than those listed above, it was discovered in some cases that he had not consulted with them while writing the papers, and submitted papers without their knowledge.

Although Mr. Maxim maintains that not all of the data is falsified, IEEE nevertheless cannot assure the integrity of papers posted by him because of his repeated false statements.

Due to the nature of this violation, reasonable effort should be made to remove all past references to the above paper, and to refrain from any future references.A multi-rate 9.953-12.5-GHz low phase noise LC oscillator was realized in a 90-GHz f/sub T/ 0.2 μm SiGe BiCMOS process. It achieves a 36% tuning range by combining a 35% open-loop frequency calibration range having a sub-0.1% residual error with a 1% closed-loop varactor frequency tuning. The oscillator gain is below 130 MHz/V, while having less than 10% variation over the entire tuning range. The varactor is realized with multiple parallel-connected cells consisting of constant capacitors and voltage-controlled resistors that bring a lower process variation and a higher quality factor in- comparison with standard diode and MOS varactors. A dual regulator architecture was used to provide both high PSRR and low output voltage noise. The supply pushing was reduced below 100 kHz/V by using a pushing cancellation circuit that balances the negative and positive voltage coefficients of the different nonlinear capacitors connected to the LC tank. A discrete-time automatic amplitude control loop using a variable tail resistor architecture was implemented to optimize the VCO's phase noise performance. The VCO specifications include 9.953-12.5-GHz frequency range, 0.1% frequency calibration error, -122 dBc/Hz phase noise at 1 MHz offset, <3 kHz 1/f/sup 3/ corner frequency, <-80 dBc spurious tones, 250×400 μm/sup 2/ die area and 5-mA bias current from a 3.3-V supply.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:41 ,  Issue: 4 )